Intel Central Processing Unit part #: AV8063801116102S R0QK Features:

• Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction / data second-level cache (L2) for each core • Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores

System Memory Support

• Two channels of DDR3 / DDR3L / DDR3L-RS memory with Unbuffered Small Outline Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per channel Note: 2 DIMMs per channel supported only in Quad-Core rPGA package only • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • System Memory Interface I/O Voltage of 1.35 V and 1.5 V • DDR3, DDR3L, and DDR3L-RS DIMMs / DRAMs running at 1.5 V • DDR3L and DDR3L-RS DIMMs / DRAMS running at 1.35 V • Support memory configurations that mix DDR3 DIMMs / DRAMs with DDR3L / DDR3L-RS DIMMs / DRAMs running at 1.5 V • 64-bit wide channels • Non-ECC, Unbuffered DDR3 / DDR3L / DDR3L-RS SO-DIMMs only • Theoretical maximum memory bandwidth of: — 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s — 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s • Processor on-die Reference Voltage (VREF) generation for both DDR3 Read (RDVREF) and Write (VREFDQ) • 1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported — Using 4Gb DRAM device technologies, the largest memory capacity possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration • Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices) • Command launch modes of 1N/2N • On-Die Termination (ODT) • Asynchronous ODT • Intel® Fast Memory Access (Intel® FMA): — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling

ITL:AV8063801116102S R0QK

AV8063801116102S R0QK